1. Technical Field
The present invention relates generally to wireless communication and wireless power transfer (WPT), and more specifically to Near-field Communication (NFC) readers optimized for high performance NFC and wireless power transfer with small antennas.
2. Background Information
NFC technology became a popular short-distant secure communication approach in recent years. NFC leverages the fast decaying magnetic field as its communication medium, and realizes a short communication distance of merely a few centimeters, which grants high security and usability.
As shown in FIG. 1, there exist two types of typical NFC interfaces, which are NFC Reader 101 and NFC Tag 102. Near-field communication is usually conducted between these two interfaces. NFC is a half-duplex communication system, which contains two communication links, i.e., Reader->Tag link 103 and Tag->Reader link 105.
Reader->Tag link 103: NFC Reader 101 generates an oscillating Magnetic Field 104 with a center frequency of 13.56 MHz as information carrier. NFC Reader 101 maintains the presence of the Magnetic Field 104 throughout the entire communication process, regardless of the active communication link. The carrier is modulated by NFC Reader 101 to transmit information for the Reader->Tag link 103. When the NFC Tag 102 is in the vicinity of the magnetic field 104, it collects the energy carried by the field, and demodulates the information superimposed on the field to retrieve information. To ensure sufficient bandwidth, the antenna quality factor of the NFC Tag 102 is sufficiently low (<30).
Tag->Reader link 105: Conventional NFC tag interfaces are passive interfaces that do not emit any radio frequency (RF) energy. They rely on the passive load modulation on Magnetic Field 104 for data transmission. Specifically, passive NFC tag interfaces modify the impedance of the load that connects to the antenna for transmission. The variation of the load impedance varies the strength of the Magnetic Field 104. This results in controlled variation of the current flowing through the reader's antenna, which can be measured to demodulate the information.
Because the NFC reader interface emits high power in communication, it is usually adopted by devices with abundant energy, such as smartphones, tablets, and POS terminals. On the other hand, NFC tag interfaces are usually employed by low power devices, like smart cards and wearable devices.
NFC Tag 102 can be configured to collect the energy carried by the oscillating magnetic field 104, to power the interface itself and other connected devices. This is called as “NFC energy harvesting,” which is widely utilized on applications like smart cards and smart tags.
FIG. 2 shows the typical architecture of conventional passive NFC tag interfaces. Antenna 201 is comprised of one or many loops of conductive wires, which receive the energy and the modulated information carried by the oscillating magnetic field. Antenna match circuit 202 transforms the impedance of Antenna 201 to a suitable value. Demodulator 203 demodulates the received signal and recovers the original information. Load Modulator 205 modulates the impedance of the load connecting to the Antenna 201 to transmit information. Data Interface 204 is connected with external components like microcontrollers (MCU) via a data bus, which is used for exchanging data and configuration. Rectifier and Regulator 206 converts the received RF energy to regulated DC (direct current) energy that could be used for powering system components.
FIG. 3 shows the typical architecture of NFC reader interfaces. Antenna 301 is comprised of one or many loops of conductive wires, which generate oscillating magnetic field, transmit, and receive NFC signals. Antenna match circuit 302 transforms the impedance of Antenna 301 to a suitable value for improving efficiency. Modulator 304 modulates the signal used for generating oscillating magnetic field according to the data to be transmitted. Antenna Driver 303 amplifies the signal Modulator 304 generated, and drives Antenna 301 via Antenna match circuit 302. To improve power efficiency, Antenna Driver 303 usually has low output impedance. Demodulator 309 measures and tracks the strength of the current flowing through Antenna 301, and demodulates the superimposed signal. MCU 307 manages the entire interface, and its tasks include: assembling and dissembling NFC frames, data integrity verification, data exchange via Data Interface 305, controlling and management of on-chip components. Data Interface 305 is the communication interface between the NFC reader and external components, and is usually in the form of SPI (Serial Peripheral Interface), I2C (Inter-Integrated Circuit), or UART (universal asynchronous receiver/transmitter). FIFO (First In First Out buffer) 306 serves as a bidirectional buffer between Data Interface 305 and MCU 307. Clock System 308 generates the necessary clocks for the NFC reader interface, including the 13.56 MHz carrier frequency. On-chip Power Supply 310 provides regulated power and reference for the NFC reader interface.
Conventional NFC system has two major disadvantages. First, passive NFC tag interface requires an antenna of a large size to realize a reasonable communication distance. Due to the weak signal generated by passive load modulation with a low-Q antenna, passive NFC tag interfaces must use sufficiently large antennas to increase the coupling between the antennas of NFC reader and passive tag interfaces. When the antenna is too small, the low coupling results even weaker passive load modulation signal that cannot be correctly received by the NFC reader. Second, the low-Q antenna systems of NFC system lead to low wireless transfer efficiency, which only allows very little power to be collected by the passive tag NFC interface (10 mW to 20 mW). Such limited power can only support very simple operations, like read/program internal memory.
Many current and most next-generation smart devices like wearable devices, smart cards, and Internet-of-Things (IoT) have small form-factors that cannot afford large NFC antennas. However, small antennas significantly limit the performance and reliability of NFC, resulting in very short communication distance and unreliable connection.
Many current and next-generation NFC applications such as wearable devices, smart cards, and smart sensors require significantly higher NFC energy harvesting capacity than current NFC products could provide, due to their sophisticated functions and high processing power. The extremely limited NFC energy harvesting capability significantly limits the performance of these devices.
To solve the weak signal problem caused by small NFC antennas, current mainstream solutions employ active modulation techniques to replace passive load modulation on the NFC tag interfaces. Active modulation techniques actively emit RF signals that do not rely on the carrier signal, a.k.a., the oscillating magnetic field. As active modulation can emit arbitrarily high power, small antennas can yield the similar communication performance as larger antennas. However, active modulation is not a perfect solution to this problem. First of all, since active modulation generates RF signals when the carrier signal is still present, it requires precise phase and frequency synchronization of the generated RF signal to the carrier frequency. This calls for complex PLL (phase-locked loop), antenna drivers, and phase tracking circuits, which greatly increase system cost and power consumption. Moreover, active modulation technology cannot support NFC energy harvesting due to its principle of operation. It requires external power to operate. Therefore, applications relying on NFC energy harvesting, like smart cards and smart sensors, are incompatible with the active modulation technology.
To mitigate the problem of limited NFC energy harvesting capability on NFC tag interfaces, current solutions actively decrease the power consumption of devices, so that the limited harvested power can still support normal operation. These solutions include employing advanced IC (integrated circuit) manufacturing techniques (e.g., from 130 nm to 90 nm process), increasing device sleep time, lowering device operating frequency, etc. However, these methods solve the problem at the expense of cost or performance.